1. Field of the Invention
The present invention relates to a circuit that drives wires for supplying drive signals that drive a plurality of controlled circuits, and to a semiconductor memory device that makes use of this drive circuit.
2. Description of the Related Art
When a plurality of controlled circuits are to be driven in a semiconductor device, a wire is provided along these plurality of controlled circuits, drive control signals are provided by a driver circuit from one end of this wire, and the plurality of controlled circuits connected to this wire are all driven at once. In this case, particularly when the wire to which the plurality of controlled circuits are connected has a large capacitive load and is driven by a driver circuit connected to one end of the wire, the shape of the drive control signals may be much flatter at the other end of the wire.
FIG. 7 is a diagram illustrating an example of a conventional drive circuit. In this example, drive control signal 11 of a signal generation circuit 10 that generates drive control signal is provided to a driver circuit 20, and one end of a wire 100 is driven at the timing of the control signal by the driver circuit 20. The wire 100 supplies the drive control signal to controlled circuits 31 through 36 provided along the wire. The controlled circuits 30 are, for example, given separate input signals that are not depicted, and perform a specific operation all at once at the timing of the drive control signal generated by the generation circuit 10 of the drive control signal.
As semiconductor devices have become more and more highly integrated in recent years, there has been a trend toward making the wire 100 thinner and narrower. In particular, the need for a multilayer construction tends to result in thinner wiring on the lower layer side, while there are limitations imposed on the width of the wiring so that it will not take up too much space. Therefore, the resistance of the wire 100 tends to be greater. Furthermore, when drive control signals are supplied to an extremely large number of the controlled circuits 30, the length of the wire 100 increases and the load capacity of the input terminals of the controlled circuits to which the wire 100 is connected results in the wire 100 having a large drive load.
FIG. 8 is a graph illustrating the signal waveform at point A, which is close to the output side of the driver circuit 20 of the wire 100, and the signal waveform at point B, which is close to the distal end on the opposite side. At point A, which is close to the driver circuit 20, the waveform is relatively sharp, as indicated by the solid line in the figure, but at point B, which is on the distal end side of the wire 100, the waveform is considerably flattened, as indicated by the broken line in the figure. This phenomenon is more pronounced the greater is the number of the controlled circuits 30 and the longer is the wire 100. Specifically, the bluntness of the waveform becomes more pronounced as the CR time constant of the wire increases. Therefore, the drive of the controlled circuit 31 positioned nearest point A in FIG. 7 is controlled at a timing equivalent to the output of the signal generation circuit 10, but the drive of the controlled circuit 36 positioned nearest point B is controlled at a timing that is considerably delayed.
When, for example, there is a need for the drive control signals to control the drive of the controlled circuits only for a short period, the timing of the control period will vary between the controlled circuits 31 and 36, and this is undesirable in terms of high-speed control within the device.